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High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS by Yun Chiu B.S.
(University of Science and Technology of China) High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS by This thesis addresses these challenges using the pipeline ADC as a demonstration platform.
Specific new design techniques. PhD Thesis University of Toronto, Low-power charge-pump based switched-capacitor circuits Alireza Nilchi PhD Thesis University of Toronto, Delta-Sigma modulators with low oversampling ratios Trevor Caldwell PhD Thesis University of Toronto, Pipelined ADC Enhancement Techniques Imran Ahmed PhD Thesis University of Toronto, Pipeline adc phd thesis - Can i buy a essay online ii In this thesis, we design a bits 5 Msample/s low-voltage pipeline ADC.
Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage.
•Typically pipeline ADC noise dominated by inter- stage gain blocks •Sub-ADC comparator noise translates into comparator threshold uncertainty and is compensated for by redundancy.Download